In an integrated circuit, commonly referred to as a chip, electrical power is distributed to the components of the chip over a network of conductors on the chip. With the increasing chip design complexity and shrinking feature size, the design and analysis of on-chip power distribution network become an extremely challenging task, which demands both high computational efficiency and accuracy for analysis tools. For analysis purposes, power distribution network (or power grid) is typically represented by a large-scale linear system in which special purpose, time-domain circuit simulation techniques are applied to identify resistive voltage drop (i.e., IR drop), electromigration and noise failures. It is a difficult task to achieve reasonable tradeoff between accuracy and performance in performing simulation of the extremely large size, flat, irregular power grids used in microprocessor designs.